1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a source line so as to connect source regions of memory cells in a non-volatile memory.
2. Description of Related Art
Typically, several source regions abutting a word line of a non-volatile memory, such as a flash memory, are electrically coupled together by a source line and is usually formed by a self-aligned source (SAS) process. The SAS process includes, using formed stacked gates as a mask, removing field oxide (FOX) structures, which are originally used to isolate the source regions. The exposed portion of the substrate is implanted with ions so that the source region are electrically coupled together to form the source line.
As the device integration increases, the FOX structure is replaced by a shallow trench isolation (STI) structure. In this situation, the STI structure causes several problems on the SAS process to form a source line. Since an aspect ratio of the STI structure is large, it leaves a trench after the STI structure is removed. When a subsequent process to form a spacer for other elements, a trench spacer is also formed on each sidewall of the trench with a large thickness. A stress then occurs and particularly occurs on the corners to cause a leakage current. Moreover, if the trench depth is large, voids may easily occurs when the trench is filled with inter-layer dielectric (ILD) layer.